Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)

Side-channel defense is crossing from software patches into native hardware, and this research exposes a critical industry illusion: the engineering cost of randomized caches is far beyond what whitepapers suggest. Technically, address-mapping randomization restructures TLB timing, cache-controller sequencing, and the address-translation pipeline. Next-gen SoCs will sacrifice 5-8% of die area to security logic, forcing a ground-up rebuild of formal-verification toolchains. EDA vendors must ship compatible verification IP by 2026 or lose the design window entirely. On compliance, the EU's NIS2 directive and financial-sector regulations now impose de facto market-access barriers on processors lacking hardware-level side-channel immunity. Chips that cannot pass these certifications face systematic exclusion from EU and North American financial markets. Strategically, ARM's MTE and Intel's TDX remain at the software/virtualization layer. Native hardware randomization is the next architectural high ground. The RISC-V camp—SiFive, Tenstorrent—is best positioned to weaponize this as a differentiator, bypassing x86/ARM patent moats. Within 18 months, security microarchitecture will harden from optional feature to mandatory baseline. The security-IP licensing market will expand 30%+, and second-tier CPU designers who fail to adapt face structural obsolescence.