PCIe 8.0 spec hits 1 TB/s of bandwidth and has new connector technology

The PCI-SIG organization announced the release of the PCIe 8.0 draft specification version 0.5, marking a significant milestone in the standard's development. This draft sets architectural requirement... Read original →

PCIe 8.0’s push to 256 GT/s exposes the breaking point of copper interconnects, forcing a full-stack I/O redesign. Upstream material suppliers must urgently develop ultra-low-loss substrates and high-frequency connectors, while AI chipmakers grapple with signal integrity and power density—NVIDIA will likely leverage Flit Mode and FEC to optimize GPU-to-GPU links, whereas AMD and Intel may embed more SerDes lanes within advanced packaging to combat channel loss. The undefined connector standard already strains supply chains; any shift toward optical or hybrid solutions would intensify CoWoS capacity bottlenecks at TSMC. U.S. export controls on advanced packaging tools could delay non-U.S. prototyping, widening the technology gap. Over the next 18 months, the industry’s central question will be whether conventional PCB processes can sustain PCIe 8.0—those who can’t will be locked out of next-gen AI infrastructure.