Outsourcing wafer handler to VDL ETG fails, ASML takes back full control - Bits&Chips

VDL ETG's exit isn't a supplier quality failure—it's a structural mismatch. At 2nm-class overlay tolerances, the wafer handler ceases to be a logistics component and becomes an opto-mechanical core subsystem. Outsourcing logic simply breaks down at this precision tier. The strategic signal dwarfs the operational one. ASML re-internalizing compresses its BOM cost buffer, marginally narrowing the competitive gap over Nikon's ArF immersion line. More critically, the 'core in-house, peripherals outsourced' playbook that served DUV is dead for EUV and High-NA. Vertical integration is now the only viable architecture. VDL ETG, stripped of its anchor customer, will likely pivot back to defense and aerospace, removing another semiconductor node from Europe's precision-machinery supply chain. The real risk window sits in the next 12–18 months: ASML rebuilding its internal handler team creates a throughput bottleneck that could lag TSMC's and Samsung's 2nm ramp schedules. The 24-month tail: expect ASML to audit every remaining 'outsourceable' subsystem—chuck, alignment, dose control—for the same integration risk. Lithography IP is irreversibly contracting back inside a single vendor's walls. The industry's modular-collaboration narrative is over.