onsemi's EliteSiC M4 Pushes Power Density Higher as Energy Demands Grow - Indovizka.com

onsemi's EliteSiC M4 is not a spec-sheet bump—it is a structural repricing of power density. The real leverage is not another few milliohms of Rds(on); it is the 20-30% thermal-area reduction that lets AI data-center 800V DC buses and EV on-board chargers shrink PCB real estate and cut BOM cost. The ripple runs both directions. Upstream, SiC substrate makers face a tighter defect-density window on 200mm wafers, squeezing Wolfspeed, Coherent, and TSMC-adjacent epitaxy lines in Taiwan, China. Downstream, packaging migrates toward double-sided cooling and embedded copper substrates; TO-247 becomes a legacy format within two product cycles. Supply-chain exposure is the quiet risk. onsemi's fabs span the US, Malaysia, and mainland China. Epitaxy reactors and ion-implant tools remain on export-control lists, so any geopolitical friction hits M4 ramp timelines directly. STMicro's Gen 3 and Infineon's CoolSiC are already shipping on 200mm substrates. If onsemi does not complete its wafer-size transition within 18 months, "generational lead" collapses into "parameter lead." The 12-24-month tail: AI power architecture migrating from 48V to 800V will outpace EVs as SiC's second growth curve. Chinese domestic players already undercut on 650V-class parts. M4 must anchor the 1200V+ tier to defend margin. The endgame is not who makes the best die—it is who codifies power density as a system-level standard first.