Industry Analysis
Onsemi's ~$1B pursuit of Ferric is not a bolt-on—it's a strategic repositioning from automotive SiC dominance into the datacenter's "last-meter" power delivery. As GPU TDP crosses 1000W and current density approaches 500A, board-level VRMs hit physical limits. IVR, sitting die-adjacent as the final regulation stage, is transitioning from an optional component to a mandatory BOM line in AI silicon. Upstream, copper interconnect and CoWoS/SoIC packaging must co-design with IVR topology; downstream, NVIDIA and AMD will embed IVR specs directly into chip design files, elevating power management from board-level engineering to chip-level IP.
MPS and Infineon will accelerate counter-moves: MPS pushing 96V→0.8V multi-stage architectures to their limit, Infineon bundling SiC+IVR solutions. The all-domestic US deal sidesteps CFIUS scrutiny, yet SiC substrate supply chains remain tethered to Taiwan, China and mainland material suppliers, while BIS controls on packaging equipment indirectly inflate manufacturing costs.
Within 12–24 months, AI power delivery will replicate the "memory wall" narrative—becoming the primary bottleneck for compute scaling. Expect 2–3 additional M&A events. IVR pricing power shifts from per-ampere to per-architecture-licensing. Ten billion is merely the entry ticket.
This page displays AI-generated summaries and metadata for research purposes. Original content belongs to the respective publishers.