One Engineer Commands AI Army for Chip Design - 동아비즈니스리뷰

This is not a story about AI-assisted design. It is the early signal that the human-capital moat protecting large fabless houses is collapsing. When one engineer orchestrates an AI pipeline that previously demanded 15-20 specialists across verification, P&R, and DFT, the cost architecture of chip design inverts. Technical cascade: Synopsys and Cadence will embed AI-native capabilities into core toolchains within 12 months, accelerating the depreciation of traditional design expertise. ARM and DesignWare IP licensing models face substitution pressure as generative models synthesize functionally equivalent blocks. Compliance exposure: If the AI stack runs on cloud inference, cross-border GDSII file flows trigger BIS export-control scrutiny. Proprietary netlists passing through third-party LLMs create exponential IP-leakage risk — not hypothetical, but already an industry incident in 2024. Market dynamics: TSMC and Samsung will internalize this as an NRE-cost weapon, further compressing fabless margins. Meanwhile, smaller design houses in China and South Korea gain asymmetric leverage against incumbents. 12-24 month tail: The "design headcount" KPI boards have relied on for a decade becomes obsolete. Expect EDA consolidation, a 30-40% contraction in junior design roles, and the emergence of "AI orchestration engineers" as the new scarce asset.