Nvidia's Huang vows to deliver 'giant amounts' of Vera Rubin — company says that 'our roadmap is intact'

NVIDIA CEO Jensen Huang dismissed reports of delays in the company's next-generation AI platform, Vera Rubin, asserting that 'giant amounts' of production are incoming. While NVIDIA confirmed producti... Read original →

Jensen Huang’s bold pledge of 'giant amounts' of Vera Rubin masks critical bottlenecks in co-packaged optics and copper midplane yields. Delays in NVL144 and cancellation of NVL72x2 reveal that beyond 3nm, system-level integration—not transistor scaling—has become the new performance ceiling. AMD’s MI300X and Google’s TPU v5e now lead in rack-scale density, exploiting NVIDIA’s packaging constraints. Geopolitical allocation of TSMC (Taiwan, China) CoWoS capacity to Apple and internal ASICs further squeezes NVIDIA’s supply. Over the next 12–24 months, failure to resolve CPO scalability may force NVIDIA to open NVLink to third-party accelerators, eroding its closed-stack advantage. This battle isn’t about FLOPS—it’s won by packaging yield and supply chain resilience.