Nvidia's custom HBM pulls Samsung onto TSMC's 3nm process, report says

Nvidia's decision to route NVHBM's base die through TSMC's 3nm node is not a sourcing tweak—it is a structural redefinition of HBM as a logic-centric system-on-package rather than a memory product. The competitive axis is shifting from "who stacks the most DRAM layers" to "who designs the best control logic on TSMC's 3nm." Samsung's "internal review before agreement" reveals genuine resistance. They are ceding design authority over the base die—the component that will carry ECC engines, on-die caches, and protocol controllers at 3nm. In effect, Samsung transitions from full-stack HBM supplier to a DRAM component vendor inside someone else's architecture. Their margin pool is structurally carved out. The cascade is inevitable: SK Hynix will face the same mandate. TSMC extends its gatekeeper role from GPU/ASIC logic into AI memory bandwidth, deepening the CoWoS bottleneck that already constrains the entire AI supply chain. For Samsung, this is dependency dressed as partnership. They lose the 3nm base die ASP and gain exposure to TSMC's capacity allocation—a single-point-of-failure risk layered on an already fragile node. 12–24 month outlook: HBM4 will cement the "memory maker does DRAM, TSMC does logic" paradigm. Pricing power and roadmap authority concentrate at the design (Nvidia) and logic-fab (TSMC) ends, while mid-stack memory vendors see their bargaining position erode further.