NVIDIA and Cisco plan 400 Gb/s-per-lane USFP module - Engineering.com

The NVIDIA-Cisco push toward 400 Gb/s-per-lane USFP is a structural reassertion of control over the AI datacenter interconnect stack, not an incremental upgrade. At 100K+ GPU cluster scale, east-west traffic has outgrown 200G/lane architectures, making the network the binding constraint on compute throughput. Technically, 400G PAM4 per lane demands InP lasers with significantly higher modulation bandwidth and DSPs whose ADC precision approaches physical limits. The USFP form factor, roughly 40% smaller than QSFP-DD, forces a complete redesign of PCB stack-up, thermal management, and connector engineering—a generational leap, not a drop-in swap. Supply chain exposure is acute: over 70% of 800G+ transceiver volume sits with mainland Chinese manufacturers, while advanced DSP and silicon-photonic foundry capacity depends on Taiwan, China. Under sustained export controls, this "design in the US, assemble in mainland China, fabricate in Taiwan, China" triangle is structurally fragile. By co-defining the standard, NVIDIA and Cisco effectively cage Broadcom and Marvell into subordinate DSP roles, building a proprietary moat around their AI infrastructure. Within 18 months, 1.6T modules will enter volume production and CPO validation on NVIDIA's next-generation platform will accelerate. The real inflection point is not the bandwidth number—it is vertical integration from optical die to system-level interconnect. NVIDIA will not tolerate the network as the "last mile" bottleneck for AI compute again.