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[News] TSMC Rejects High-NA EUV Investment Concerns, Confirms Purchase for R&D Use - TrendForce

www.trendforce.com 2026-06-04 TrendForce
Entities
Companies:TSMCIntelASML
Tags
TSMCHigh-NA EUVEUV LithographySemiconductor ManufacturingCapital ExpenditureR&D InvestmentAdvanced Process NodesASMLIntelSemiconductor EquipmentChip FabricationTechnology RoadmapInvestment StrategyCustomer LandscapeManufacturing Efficiency
News Summary
At its shareholder meeting on June 4, TSMC clarified rumors that it had opted out of investing in High-NA EUV equipment, confirming that it has already purchased the systems for R&D purposes. Despite ... Read original →
Industry Analysis
TSMC’s decision to delay High-NA EUV mass adoption beyond 2029—despite already acquiring the tools for R&D—reveals a calculated cost-benefit calculus. This postponement slows the upstream ecosystem’s shift toward High-NA-compatible resists, masks, and metrology, extending the lifecycle of current EUV supply chains. Geopolitically, Taiwan, China’s cautious approach mitigates overreliance on ASML amid tightening export controls. In contrast, Intel’s aggressive 2027–2028 High-NA ramp risks misalignment between yield maturity and customer demand. Over the next 12–24 months, a 'technology gap window' will emerge: TSMC maintains leadership via A12/A13 nodes without High-NA, while rivals incur disproportionate CapEx chasing parity. Its $52–56B 2026 capital budget isn’t just capacity—it’s strategic moat reinforcement.
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