New technique controls exactly where 2D semiconductor crystals grow - Nanowerk

Precise positional control of 2D semiconductor crystal growth marks the threshold where materials science becomes device engineering. For a decade, MoS2 and WS2 mobility benchmarks kept improving while yield remained hostage to "where does the crystal land"—a bottleneck eerily parallel to the GaN-on-Si substrate-matching crisis of 2008. The ripple effect cuts two ways. Upstream, CVD thermal-field uniformity and precursor partial-pressure windows will become the next battleground for Lam Research and ASM International. Downstream, repeatable single-domain positioning could slash interface defect density between 2D channels and 3D FinFETs by an order of magnitude, forcing a rethink of post-EUV architecture choices. Compliance risk is non-trivial. High-precision growth parameters—temperature gradients, gas-ratio windows—are prime candidates for export-control listings, echoing the 2022 precursor-chemicals episode. Lines dependent on imported substrates and specialty gases will see supply-chain redundancy costs surface within 18 months. Strategically, Intel's 2D-FET roadmap and TSMC's CFET both treat 2D materials as Plan B. If this work scales, Samsung will accelerate vertical-channel 2D pilot validation, while the Academia Sinica–ITRI pipeline in Taiwan, China could field a pilot line within 6-12 months, compressing the window for incumbents. The 12-24-month tail: the real signal is not one paper but whether it triggers the "position control → patterning → wafer-level integration" cascade. A first 2D pilot line before 2026 would reprice the entire advanced-packaging and interconnect ecosystem.