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New Semiconductor Tech Slashes AI Power from the Cloud to the Edge - EEJournal

www.eejournal.com 2026-09-10 EEJournal
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Semiconductor TechnologyAI ComputePower OptimizationCloud AIEdge ComputingChip DesignLow Power TechnologyAI AcceleratorTSMC3nm ProcessComputational ArchitectureChip Performance
News Summary
On September 10, 2026, EEJournal reported on a new semiconductor technology developed by Velaura that significantly reduces AI compute power consumption across both cloud and edge environments. The co... Read original →
Industry Analysis
Velaura’s Titan Core technology slashes power consumption in MAC and MATMUL units by 2–4 times through subthreshold operation, directly challenging the core energy inefficiencies in AI compute chips. This innovation reshapes the entire supply chain from TSMC’s 3nm process to edge devices, particularly impacting low-power chip vendors like Ambiq. The breakthrough undermines traditional high-performance computing models, forcing cloud providers to reassess data center energy budgets. The company’s prior experience in Bitcoin mining hardware validates its scalability and manufacturing readiness. If widely adopted, this approach will accelerate the shift toward more efficient compute architectures, boosting edge AI deployment. However, reliance on TSMC’s 3nm process introduces geopolitical risks amid tightening semiconductor regulations. Within 12 months, mainstream adoption could spark a new round of competition in AI chip performance vs. power efficiency, with low-power XPUs emerging as the preferred architecture.
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