Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)

This is not another paper—it is the quiet re-architecture of post-CMOS memory. Technical cascade: NEMS switches replace charge retention with mechanical state, simultaneously sidestepping eDRAM hold-time fragility and SRAM area bloat. If gain-cell density breaks below 0.02 μm², SoC cache hierarchies fracture from a binary SRAM/DRAM model into a three-tier stack. Upstream, sub-100 nm silicon release and wafer-level bonding will pull hard demand for advanced dry-etch and hybrid-bonding equipment. Compliance & supply chain: Samsung and Intel co-authoring signals a production roadmap, not a lab curiosity. Yet NEMS micro-fabrication overlaps with MEMS sensor lines. If BIS extends export controls to sub-100 nm MEMS etch tools, foundries in Taiwan, China and mainland fabs face a two-to-three-year replication lag. Market dynamics: Micron's eDRAM moat is being undercut at the architectural level. Samsung leverages this to lock in AI-GPU foundry stickiness; Intel deploys it as a differentiation narrative amid 18A yield struggles. The real wildcard is TSMC—embedding NEMS cells into CoWoS shifts competition from die-level to package-level. Outlook: The next 12-24 months will be dominated by pilot-line validation and patent fencing. The long-tail effect, however, extends far beyond memory: if NEMS switches migrate into logic gates, the CMOS scaling roadmap faces a structural break by 2030.