Monolithic III-N complementary logic - Semiconductor Today

The monolithic III-N complementary logic milestone marks the point where p-type channel devices cross from academic curiosity to engineering viability. For two decades, GaN HEMTs have dominated RF power, yet logic processing remained tethered to silicon CMOS — a heterogeneous architecture that hits structural walls in parasitic capacitance and thermal coupling at millimeter-wave frequencies. Integrating nMOS and pMOS on a single III-N substrate rewrites the architectural playbook for RF front-ends and mmWave switch matrices. Upstream, AlGaN p-type epitaxy carrier mobility becomes the new bottleneck, forcing MOCVD process windows to be recalibrated. Infineon, Qorvo, and ROHM's IDM strategies will collide with China's state-backed GaN capacity in a race to mass-produce p-type III-N first. On compliance, epitaxy equipment export controls are tightening, but the IP moat around complementary logic far exceeds that of single n-type devices — patent battles will center on p-type design rules, not equipment restrictions. 12–24 month outlook: expect first III-N CMOS test chips by 2026, mmWave prototype validation by 2027. The longer tail is more consequential: if III-N logic delivers superior power efficiency above 400 GHz versus InP, silicon-based RF front-ends face systematic displacement in the 6G cycle. This is a generational materials shift, not an incremental upgrade.