Micron plans to use wafer bonding and High-NA EUV for next-gen DRAM

Micron's rejection of 4F2 in favor of wafer bonding plus High-NA EUV is not a process tweak—it is a paradigm shift that yanks DRAM out of the 2D scaling race and into architectural 3D stacking. The supply-chain ripple is immediate: bonding mandates separate fabrication of peripheral logic and cell arrays, making ASML lithography, Besi hybrid-bonding tools, and sub-100nm wafers from SUMCO and Shin-Etsu the new chokepoints. It echoes Samsung's 2012 SAQP equipment bottleneck, but with a far more extreme single-vendor dependency. Strategically, this dismantles Samsung's CBA-plus-4F2 monopoly narrative. If Micron and SK Hynix converge on bonding architectures, Samsung risks becoming a technology island. The deeper play is HBM: with HBM4 exceeding 16 stacks by 2026, bonding shifts from optional to mandatory—Micron is positioning for HBM5. Over 12–24 months, High-NA tools at $400M+ and 18-month yield ramps mean Micron's production may lag Samsung by one node, yet architectural generational gaps can erase that timeline. The structural wildcard: once DRAM goes 3D, NAND's density moat erodes, and Kioxia and SanDisk face their first genuine pricing-power threat from the DRAM side.