Microchip expands data centre portfolio to support AI-driven infrastructure - New Electronics

Microchip's data center push is not a product-line extension—it is an analog chipmaker seizing pricing power over the connectivity layer in a narrative dominated by digital compute. Technically, AI cluster bottlenecks have shifted from raw FLOPS to interconnect bandwidth and power density. Leveraging Microsemi's SerDes and Ethernet switching IP, Microchip is almost certainly targeting retimers, CXL controllers, and high-density PMICs for GPU-to-GPU links. This pulls advanced packaging capacity upstream and slots directly into Supermicro and Dell BOMs, eroding TI's and ADI's industrial connectivity share. On compliance, 112G/224G SerDes components are creeping into export-control scrutiny. If back-end fabs sit in Taiwan, China or Malaysia, the 2025 end-user traceability tightening will inflate compliance costs materially, especially if any customer touches a sanctioned entity. Competitively, Broadcom owns custom ASICs, but Microchip's embedded DNA creates an MCU-plus-connectivity bundle with ecosystem lock-in at edge-inference nodes—something TI cannot replicate. NXP, if it responds, will likely orbit NVLink periphery rather than engage head-on. The 18-month outlook: CXL 3.0 standardization will spawn a new memory-expansion controller market. As AI shifts from training to inference, node counts explode while per-node power drops. The connectivity-plus-power analog market re-inflates—and that is precisely Microchip's home turf.