Memory In Physical AI

LPDDR6's real significance isn't "faster phone RAM"—it redraws the compute boundary for Physical AI. When foundation models migrate to robotic joints and edge nodes, memory bandwidth stops being a spec-sheet number and becomes a survival constraint. On the technical chain, LPDDR6's wider data buses force a redesign of SoC memory controllers, creating a new value anchor for TSMC (Taiwan, China) in mobile advanced packaging. The Samsung–SK Hynix 1b/1c nm race accelerates, but the core tension shifts from "who ships first" to "who balances HBM and LPDDR6 capacity simultaneously." Supply-chain risk is structural. US export controls on advanced memory create a compliance fault line: when Physical AI devices deploy in critical infrastructure, memory provenance becomes a new audit vector. CXMT has narrowed the DDR5 gap, but LPDDR6's JEDEC patent moat and controller-IP ecosystem lock-in keep it out of the high-end Physical AI supply chain for now. Strategically, Samsung will likely lock LPDDR6 allocation to Apple and Tesla's autonomous-driving silicon to own the reference scenario. SK Hynix may leverage HBM stacking know-how for differentiation. Micron's existential risk: if the Physical AI inflection hits in 2026–2027 and its mobile DRAM share keeps eroding, it misses the "memory-as-compute" pricing-power shift entirely. 12–24-month tail effect: LPDDR6 becomes the single largest memory line-item in Physical AI BOMs. As humanoid-robot shipments jump from thousands to tens of thousands, memory pricing logic flips from "cyclical commodity" to "strategic resource"—and whoever controls LPDDR6 capacity wields pricing power approaching today's GPU.