Memory bottlenecks drive HBM shift to 8-layer stacks

Core thesis: the industry is trading density for yield, exposing that HBM's physical scaling roadmap is hitting its ceiling sooner than projected. An 8-layer stack reduces TSV alignment tolerance and per-stack thermal density, directly improving wafer-level yield at SK Hynix and Samsung. But the paradox is stark: NVIDIA's B300 architecture was architected around 12-to-16-layer HBM3E. Downgrading to 8 layers forces either a bandwidth haircut or a wider interconnect topology — making TSMC's CoWoS packaging (Taiwan, China) the new chokepoint. For custom ASIC players — Google TPU, Amazon Trainium, Microsoft Maia — this is a net positive. Inference workloads tolerate lower stack heights far better than training does. The H2 2027 timeline signals the 12/16-layer yield problem is structural, not cyclical. Strategic positioning: SK Hynix deepens its yield moat in the 8-layer segment, consolidating pricing power. Samsung's HBM3E qualification struggles get diluted as the market standard resets lower. Micron's HBM3E ramp timing aligns more favorably. 12-to-24-month trajectory: HBM4 (16-layer) timelines will slip. CXL 3.0 memory pooling accelerates as a bandwidth supplement. The inference market will spawn an "HBM-lite" tier, where 8 layers becomes the default configuration rather than a compromise.