Marvell unveils second-generation Structera X memory expanders for AI inference - Crypto Briefing

Marvell isn't selling a memory chip—it's forcing an architectural decoupling. The 2nd-gen Structera X mirrors the 2010s CPU-GPU separation, but applied to memory: KV cache and cold weights get offloaded from HBM dies onto an interconnect layer. Upstream, SK Hynix and Samsung's HBM4 pricing power erodes when equivalent capacity no longer requires die-level stacking. Downstream, NVIDIA's NVLink-C2C and AMD's Infinity Fabric assume monolithic memory coupling; Marvell forces them to either natively integrate CXL 3.0 or cede the inference cost-efficiency tier. On compliance: US BIS restrictions on 128GB+ HBM shipments already constrain China-bound deployments. A CXL-based expander achieving equivalent capacity through interconnect sits in a regulatory gray zone—precisely the 'compliance workaround' path that Beijing's AI buyers will scrutinize. Marvell's foundry dependency on TSMC (Taiwan, China) adds a single-point-of-failure risk. Competitive read: Astera Labs and Montage Technology will compress their 2025-26 product cycles. NVIDIA's most probable counter is embedding a CXL 3.0 controller into the Rubin/B300 generation, eliminating the third-party expander value prop entirely. 12-24 month trajectory: memory pooling becomes the default inference architecture. The 30-40% HBM premium in AI server BOM compresses. Expect 2-3 M&A events in the CXL/interconnect space by 2027.