Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference - 01net

Marvell's real play isn't the six-channel spec—it's forcing CXL from optional accelerator into architectural necessity. When a 70B model's KV cache outgrows 192GB of HBM, pooled CXL memory stops being a nice-to-have and becomes the survival line for inference economics. The supply-chain ripple is immediate: six channels per die means 256GB+ of low-latency external memory, structurally eroding SK Hynix and Samsung's HBM pricing moat. If CXL DDR5 delivers adequate bandwidth at roughly one-fifth the cost, the HBM premium thesis cracks. Competitively, Astera Labs' Scorpio tops out at four-channel CXL 3.1. Marvell's first-to-market six-channel 3.2 locks in the performance-ceiling narrative during hyperscaler selection windows. NVIDIA's NVLink-C2C and AMD's Infinity Fabric remain closed alternatives, but CXL's open ecosystem is penetrating x86 datacenters faster than either proprietary fabric. Geopolitical risk: CXL IP licensing is heavily US-concentrated. Chinese AI chip designers without 3.2-generation IP access face a compute-without-coherent-memory architectural gap by 2026. Twelve-to-twenty-four-month outlook: CXL 3.2 enters OCP standard BOMs. Memory scheduling silicon becomes the third critical AI infrastructure category after GPU and HBM. The Marvell-Astera duopoly is essentially locked.