Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Hardware Security - Marvell Technology

This is not a security standardization exercise—it is a reallocation of silicon-layer governance. Marvell's choice of OCP over JEDEC is deliberate: bypass Intel/AMD's processor-level security stacks and embed a 'neutral' trust anchor at the interconnect and custom-silicon layer. Once hardware root-of-trust, secure boot chains, and cross-chip attestation are standardized, upstream RISC-V security extensions and ARM CCA deployment paths get redefined. Downstream, hyperscaler multi-tenant isolation migrates from software to silicon, cutting hypervisor overhead—but ASIC designers face 30-50% higher security IP certification costs. Compliance: ahead of the EU Cyber Resilience Act's 2027 enforcement, OCP specs will likely become the de facto reference architecture. For OSAT and module vendors in Taiwan, China and Southeast Asia, dual FIPS 140-3 plus OCP certification will compress margins by 5-8 points. The tell: Intel, NVIDIA, AMD are all absent. NVIDIA's Confidential Computing is GPU-locked; Intel's TDX is x86-bound. Neither wants security standards to be platform-agnostic. Expect the ARM camp to launch a competing attestation spec within 12 months—creating a two-track landscape. 12-24 month tail: AI inference clusters will be the first mandatory adoption scenario. When model weights traverse nodes, hardware-level attestation is the only zero-trust verification path. Marvell locks in a 'toll booth' position for custom-silicon security IP, and its interconnect products gain structural pricing power through standard binding.