Majestic Labs Raises $100M for Memory Pooling AI Server

Majestic Labs, an AI chip startup, has raised $100 million in Series A funding to advance its memory-pooling AI server architecture. The company aims to overcome the limitations of current HBM-based s... Read original →

Majestic Labs’ $100M raise signals a strategic pivot in AI infrastructure—from HBM stacking to disaggregated memory-compute architectures. By replacing costly HBM with pooled LPDDR via proprietary interconnects, it pressures SK Hynix and Micron’s premium memory segments and compels TSMC (Taiwan, China) to refine 3nm EUV economics for chiplet-based packaging. Geopolitically, while U.S. export controls on advanced packaging tools pose supply chain risks, Majestic’s avoidance of CoWoS and GAA transistors grants it regulatory buffer. In response, NVIDIA’s Grace Hopper may face efficiency-based competition, likely accelerating AMD and Intel’s CXL ecosystem investments. If tape-outs succeed in 2024, memory pooling could become the new baseline for AI inference servers—particularly in low-latency domains like high-frequency trading—marking the first credible crack in GPU-centric dominance.