M6 deep dive: A brilliant 2nm design held back by bandwidth - Macworld

M6's 2nm design being throttled by bandwidth exposes a structural blind spot the industry has ignored: transistor density jumps 30-40% per node, yet I/O and interconnect scaling has fallen dangerously behind. TSMC's N2 GAA and backside power delivery solve the compute problem but not the feed problem—data movement can't keep pace with throughput, diluting 2nm's efficiency gains in AI inference workloads. Ripple effects are cascading through the supply chain. Upstream, N2 yield and CoWoS-L packaging capacity have become the scarcest bottleneck, with Apple, AMD, and NVIDIA competing for the same wafer slots. Downstream, Apple is forced to accelerate LPDDR6 adoption, and M7 may introduce HBM-like on-package stacking—reshaping its negotiating leverage with SK Hynix and Samsung. On the competitive front, Intel's 18A and AMD's Zen 6, if they deploy more aggressive memory bandwidth architectures on N3P, will compress M6's nominal process lead. Apple's moat is migrating from node leadership to system-level bandwidth orchestration. Over the next 18 months, the bandwidth wall will replace the process wall as the primary constraint for mobile SoCs. Apple will likely ship an M7 with a custom memory controller by H2 2026, with TSMC's N2A backside power architecture as the critical enabler.