Linux 7.4 Preps CXL For Very Neat Dynamic Capacity Devices "DCD" - Phoronix

CXL DCD entering the Linux mainline is not a driver patch—it is a paradigm shift from static allocation to runtime memory elasticity. Technical cascade: DCD lets CXL memory devices scale capacity without reboot, forcing hypervisor hot-migration logic to be rewritten. Samsung, SK Hynix, and Micron must redesign CXL module firmware to expose capacity-change events. Astera Labs' CXL switches evolve from bandwidth movers into capacity orchestration hubs. AWS and Azure push pooling from coarse NUMA to page-level dynamic allocation, dismantling two decades of DIMM-slot binding. Supply chain: CXL carries no export-control risk per se, but CXL 3.x depends on PCIe 6.0 PHY IP concentrated at MediaTek and Realtek in Taiwan, China, plus advanced packaging at Micron and Samsung—a "software-open, hardware-closed" structural fragility. Market dynamics: Native Linux DCD erases Intel's last CXL software-stack moat. AMD EPYC 9005 already ships CXL 2.0; with kernel-level DCD, AMD unlocks equivalent elasticity without proprietary drivers. Astera Labs (>60% CXL switch share) is the surest beneficiary, but its valuation already prices in CXL 2.0. Outlook: Within 18 months, DCD becomes a cloud-vendor SLA commitment. Memory-as-a-Service replaces per-slot billing. The HBM/CXL-DRAM boundary blurs in AI inference. By 2026, CXL pooling captures 15-20% of server-memory incremental demand; the biggest losers are secondary cloud operators built on overcommit arbitrage.