Lightmatter CEO: AI’s Next Scaling Challenge Is Interconnect, Not Compute

In a recent podcast interview, Lightmatter CEO Nick Harris highlights that as AI shifts from compute-bound to memory and interconnect-bound workloads, optical interconnect technology is emerging as a ... Read original →

As AI scaling hits interconnect bottlenecks, optical I/O transitions from optional to essential. Lightmatter’s pivot from photonic computing to 3D co-packaged optics reflects a strategic recognition: copper interconnects collapse beyond 3nm due to RC delay and power density, while EUV economics make further transistor scaling unsustainable. This shift pressures TSMC and Intel to accelerate silicon photonics integration and compels NVIDIA to embed optical I/O deeply in post-Blackwell architectures. Geopolitically, despite U.S. CHIPS Act support for domestic advanced packaging, reliance on Asian-sourced InP and specialty materials introduces supply chain fragility, potentially inflating compliance costs by over 20%. Within 18 months, startups with electro-optical co-design capabilities will become prime M&A targets, while legacy SerDes IP vendors face severe valuation compression. Optical interconnect is no longer just a bandwidth enabler—it’s the new battleground for AI chip architecture sovereignty.