Lab To Fab At Wafer-scale For SiC - The National Tribune

The transition from laboratory-scale research to wafer-scale fabrication represents one of the most critical inflection points in the silicon carbide semiconductor industry. While SiC's superior elect... Read original →

The 200mm SiC transition is not a scale-up—it is a renegotiation of material physics. Expanding the PVT thermal field from 150mm to 200mm non-linearly worsens edge-to-center temperature gradients, compressing the BPD convergence window to a razor-thin band. This directly caps epitaxial uniformity and ion-implant junction depth consistency, the two parameters governing RDS(on) spread across a wafer. Wolfspeed's 200mm bet is a classic 'build capacity, find customers' capital gamble. Infineon and ST are playing a different game: 150mm epitaxy optimization plus device architecture iteration, trading time for yield. ROHM's vertical integration offers structural cost advantages, yet substrate self-sufficiency remains the Achilles' heel. The real wildcard is geopolitical. SiC substrate capacity is concentrated in the US, Japan, and Europe. If export-control logic extends from lithography equipment to wide-bandgap materials, global EV supply chains face a 'material cutoff' far more severe than chip shortages—substrate growth cycles span weeks, making supplier switching nearly impossible. Within 18 months, whether 200mm yield crosses 85% will be the dividing line. Miss it, and Wolfspeed's capex becomes a balance-sheet time bomb. Hit it, and SiC device costs break below the 3x Si IGBT premium by 2026, pushing SiC adoption into the $20K EV segment. IDMs without substrate sovereignty will lose pricing power to Coherent and emerging substrate players in Taiwan, China and mainland China.