Keeping Security Algorithms Current Is Getting Harder

As cybersecurity threats evolve at an unprecedented pace, protecting security algorithms throughout the design, manufacturing, and supply chain lifecycle is becoming increasingly complex. Security alg... Read original →

Hardware security is shifting from optional feature to architectural imperative. At sub-3nm nodes with pervasive EUV, physical tamper resistance costs are soaring, compelling IP vendors like Rambus and Synopsys to hardwire PUFs and post-quantum algorithms into Root-of-Trust blocks. This triggers a cascade: EDA flows must embed HBOM traceability, while Arm must bake cryptographic agility into ISA extensions. Compliance-wise, NIST’s PQC standardization will force automotive and defense chips to lock in decade-long update pathways, inflating BOM costs by 15%+. Strategically, Apple and Samsung leverage in-house SoCs to vertically integrate security, marginalizing third-party solutions; Cadence and Keysight respond by hardening SBOM validation into signoff flows. Within 18 months, chips lacking native hardware roots of trust will be blacklisted by hyperscalers—security is no longer a spec, but a supply chain passport.