Jevons’ Paradox and the Silicon Roadmap

Jevons' Paradox in compute is more brutal than the textbook: doubling performance-per-watt is instantly swallowed by tenfold AI inference expansion. The inflection point isn't transistor scaling—it's packaging and interconnect. CoWoS capacity, HBM stack density, and optical I/O bandwidth are the "post-Moore" variables determining which architectures retain value through 2026 and which become stranded assets. On the tech stack, the 2nm GAA yield ramp (2025Q3–2026Q2) forces a value-versus-risk tradeoff between 3nm and 2nm. If CXL 3.0 memory pooling lands on schedule, it structurally undermines HBM's pricing premium—SK Hynix and Samsung's HBM3E margin moat will erode. Supply-chain risk is no longer a footnote. Advanced-node capacity remains concentrated in Taiwan, China and South Korea, while tightening EUV and EDA controls have turned "technical compliance" into a hidden BOM tax. The CHIPS Act cycle and mainland China's mature-node expansion create a bifurcated ecosystem; fabless firms now maintain dual verification stacks, inflating NRE by 15–25%. Competitively, NVIDIA's CUDA moat faces flanking pressure from custom ASICs. AMD's MI350 bets on ROCm maturity, but the window is 12 months, not 24. The 12–24-month long tail: optical interconnect enters CoWoS-L production in 2026H1, breaking copper's bandwidth ceiling and triggering a PCB and connector re-rating. Sub-7nm non-AI logic will likely see a 2019-style capacity purge. The silicon roadmap is not a multiple-choice exam—it's an elimination tournament.