Japanese chipmaker Rapidus targets Taiwan’s chip cluster model, plans 3 more Hokkaido plants

Rapidus isn't building fabs—it's attempting to compress 25 years of Hsinchu's ecosystem gravity into a five-year government-subsidized sprint. Three Hokkaido plants are the anchor; the real play is pulling EDA, photoresist, and advanced packaging into a 50-kilometer radius. IBM Japan's co-located office isn't a support desk—it's a lock on heterogeneous integration and HPC workloads, the true post-Moore battleground. Technically, three plants signal a shift from 2nm validation to volume ramp. But GAA architecture demands lithography precision two orders of magnitude beyond 5nm, and ASML's High-NA EUV delivery slots are already booked through 2027. Without securing that equipment window, Rapidus risks three underutilized shells—a capital black hole dressed as industrial policy. Competitively, Samsung's P4 and Intel's 18A are racing for 2nm first-mover. Rapidus's edge isn't the node; it's the "Japanese materials + US equipment + Taiwan, China cluster model" triangle. But semiconductor ecosystems emerge organically. No METI grant accelerates the tacit knowledge transfer that took TSMC two decades to build in Hsinchu. The 12-24 month tell: can Rapidus push 2nm yield past 70% by end of 2026? If not, the capex narrative collapses. IBM's positioning, meanwhile, signals the long-tail is in packaging, not patterning.