Introducing Build-A-Chip-Bench: From Workload Specification to GDS

Build-A-Chip-Bench is not a benchmark — it is a redefinition of the industry's unit of measurement. Anchoring AI-agent evaluation on open-source PDK and open-source EDA (OpenROAD, Yosys) sends an unambiguous signal: the design "brain" is becoming software, not a licensed tool suite. Synopsys and Cadence's moat is being redrawn from tool ownership to model-plus-data-flywheel. The critical caveat: the benchmark runs on a simplified process node. Production PDKs from TSMC (Taiwan, China) or Samsung at 3nm/5nm carry hundreds of design rules that no open-source flow handles. The gap between benchmark score and production yield is the single variable that will determine whether AI agents ever cross the tapeout threshold. Under export-control pressure, open-source EDA flows are no longer a cost play — they are a supply-chain resilience hedge. Yet cross-PDK generalization of AI agents introduces yield unpredictability that fabless firms simply cannot absorb. Training on one process, deploying on another, is handing yield to probability. Within 12–24 months, expect the first AI-native standard-cell libraries to enter tapeout, and the benchmark to expand into multi-node, multi-corner evaluation. The real disruption is not AI replacing designers — it is AI converting chip design from a craft into a reproducible industrial product.