Intel Tech Chief Says Being A Few Percent Behind TSMC On Performance Doesn’t Matter, But Catching Up In Scale Will Be Slow – VP Asserts High NA EUV Is The Right Choice - Wccftech

The real signal in Intel's VP remark isn't "a few percent performance gap is acceptable"—it's that scale catch-up is a slow variable, the existential weakness of their foundry strategy. Betting on High NA EUV compresses the sub-2nm yield window into a "get it right once" gamble. With ASML's single system near $400M and the photoresist/detection chain still maturing, Intel's 14A (2027) yield will be tightly coupled to ASML's iteration cadence. Against TSMC's N2 locked for 2025 volume in Taiwan, China, the timeline gap dwarfs any "few percentage points" delta. Scale is fundamentally an ecosystem lock-in problem—EDA, IP libraries, CoWoS synergy create switching costs no yield milestone alone can break. If competitive external capacity isn't delivered before 2026, the foundry business degrades into internal contract manufacturing, fundamentally altering valuation. Tightening lithography export controls to China make High NA systems virtually impossible to flow there, paradoxically reinforcing the "compliant capacity" premium. But deployment in Ohio and Arizona pushes capex well beyond guidance. 12-24 month call: 18A external first delivery likely Q1-Q2 2026; 50K WPM still needs 18+ months. TSMC will use the N2 window to lock Apple and NVIDIA 2nm orders. The real High NA inflection is 2027—if 14A yield doesn't breach 85%, the "sole US advanced node" narrative faces capital repricing.