Intel eyes dual-side power in 1.4nm push against TSMC

Intel’s bet on dual-side power delivery at the 1.4nm node reflects a high-stakes maneuver as transistor scaling nears physical limits. This forces EDA, photoresist, and interconnect material suppliers to rapidly adapt to 3D current pathways, raising R&D barriers across the upstream ecosystem. With U.S. CHIPS Act subsidies expected to taper, failure to achieve yield breakthroughs by 2027 would severely strain Intel’s capex and supply chain resilience. TSMC will likely counter with incremental refinements to its existing backside power delivery (BSPDN), avoiding radical fab retooling, while Samsung may be compelled to follow—deepening its financial stress. Over the next 18 months, advanced packaging and chiplet integration will become critical buffers against process-node setbacks. The real battleground has shifted from raw node performance to system-level power efficiency and manufacturing robustness.