Intel CTO: process gap with TSMC down to a few points, but scale still lags

Ranade's "few percentage points" framing invites a misread: the market hears parity. The real signal is the second clause — scale. Process is a 0-to-1 problem; yield consistency, wafer throughput, and PDK ecosystem lock-in are the 1-to-N moat. TSMC's true barrier isn't the transistor. It's the hundreds of billions of transistor-level validations Apple, NVIDIA, and AMD have accumulated on its nodes over a decade. No 18A yield target erases that design inertia overnight. On the supply chain, a credible 18A/14A breaks the single-source assumption in ASML's high-NA EUV calibration data, pressuring Carl Zeiss's pricing power. EDA vendors — Synopsys, Cadence — face forced dual-PDK maintenance, restructuring their cost base. Geopolitically, the $8.5B CHIPS allocation is a hedge, not a subsidy. Washington needs a 2nm-class line that doesn't route through Taiwan, China. Ranade's admission of a scale gap is the exact bottleneck. TSMC's Arizona ramp already demonstrates that leaving the home supply chain stretches yield curves by 18 to 24 months. Competitive response: TSMC will likely front-run N2A and lock customers into five-year capacity reservations. Samsung remains the low-cost fallback; its foundry credibility won't recover this cycle. 12-24 month call: the process delta narrows to near-zero; the scale delta holds until 2027 at the earliest. Markets will price Intel Foundry as a strategic option, not a commercial rival, until two or more hyperscaler external wins land.