Intel chief says US-China chip gap is narrowing - Bangkok Post

Intel's CEO isn't offering diplomacy—he's confirming a structural shift. China's self-sufficiency in mature nodes (28nm+) has crossed 70%, RISC-V is eroding ARM's share in IoT and automotive MCUs, and chiplet-based advanced packaging is the pragmatic bypass around EUV dependency. This isn't catch-up; it's a lane change. The real chokepoints aren't transistor scaling but the upstream stack: EDA toolchains, photoresists, specialty gases. Domestic substitution is diluting these bottlenecks but hasn't eliminated them. On compliance, the marginal deterrence of US export controls is fading. Firms now run dual-track supply chains—de-risking from China while maintaining China-facing operations—pushing compliance costs to 3-5% of revenue. TSMC's North American and European fabs are geopolitical hedges, not efficiency plays. Over the next 18 months: expect regional oversupply in 28-90nm nodes and an inevitable price war. Advanced packaging (CoWoS, Foveros) will be the true strategic battleground. If Intel's foundry can't lock in 3nm design wins by 2026, IDM 2.0 becomes a structural failure, not a timing issue.