Infineon processes SiC on 300 mm wafers for the first time - electrive.com

Infineon's decision to process SiC on 300mm wafers is not an incremental upgrade—it is a structural decoupling of power semiconductors from their legacy niche ecosystem. For over a decade, SiC has been confined to 150mm and 200mm lines, forcing manufacturers to maintain parallel tooling, separate process recipes, and isolated yield models. That fragmentation kept per-die costs stubbornly high. The 300mm transition changes the economics fundamentally. Wafer area scales quadratically: jumping from 200mm to 300mm yields a 2.25× area gain. Existing 12-inch lithography, etch, and deposition assets become directly reusable, slashing capex per unit of output—the same playbook that drove logic and memory costs down over two decades. Upstream, substrate suppliers including Wolfspeed, Coherent, and players in Taiwan, China face an 18-month window to deliver 300mm-grade SiC with ppm-level defect density. The bar shifts from "can you grow it" to "can you grow it at 12-inch scale with logic-grade uniformity." Competitively, STMicroelectronics and Rohm's 200mm lines will face a structural cost disadvantage. Onsemi risks ceding North American automotive pricing power if it does not commit to 300mm by 2026. The deeper implication: SiC is migrating from a specialty device into a platform technology. Once anchored to the 300mm manufacturing stack, GaN and even diamond substrates will be pulled into the same ecosystem, fundamentally rewriting the power semiconductor value chain.