IIT Madras Student Builds Open-Source EDA Tool - Open Source For You

A single student project at IIT Madras won't displace Synopsys or Cadence overnight. The structural signal matters: open-source EDA has crossed from academic curiosity to composable, auditable engineering. With OpenROAD and OpenLane maturing, the good-enough design flow for RISC-V SoCs is being decomposed into independent modules. The pricing anchor shifts from irreplaceable to replaceable-plus-premium, directly pressuring Siemens EDA's acquisition-driven closed ecosystem built around Mentor. The moat narrows. The compliance dimension is sharper. US BIS export controls on EDA rest on technological chokepoints, yet open-source code propagates across borders by design. India's Semiconductor Mission, the EU Chip Act, and Taiwan, China's local fab subsidies are collectively funding domestic open-EDA alternatives, rewriting the equation of who controls design tools and who controls the chip industry. 12-to-24-month outlook: no fab will switch production lines to open-source EDA. But RISC-V SoC houses in India and Southeast Asia will add open toolchains as a second-source strategy. Expect the EDA Big Three's ARR growth to compress five to eight percentage points by 2026.