IC Security Threats Spike With Quantum, AI, And Automotive

Entities

Companies:TSMC NVIDIA Secure-IC Cadence Synopsys Synaptics Rambus Keysight EDA

People:Jensen Huang Sylvain Guilley Dana Neustadter David Garrett Scott Best Yan-Taro Clochard Durga Ramachandran

Technologies:3nm EUV Post-Quantum Cryptography Digital Signatures Side-Channel Attack Fault Injection Secure Boot Hardware Isolation

Tags

Chip Security Quantum Computing Post-Quantum Cryptography Automotive Chips Supply Chain Security Hardware Security AI Cyber Threats Digital Signatures NIST Standards Trust Boundaries Silicon Architecture Security by Design

News Summary

The rapid advancement of quantum computing, AI, and automotive electronics has led to a significant surge in chip security threats. Industry experts emphasize that current challenges have shifted from... Read original →

Industry Analysis

Quantum and AI-driven IC security threats have evolved from theoretical concerns into hard architectural constraints. At 3nm and below, EUV complexity combined with multi-vendor IP integration exponentially expands attack surfaces via side channels and fault injection—especially critical in automotive systems designed to operate for 15+ years, where hardware isolation and secure boot must be architected at RTL. While NIST’s first post-quantum cryptography (PQC) standards are published, their direct implementation in area- and power-constrained automotive SoCs remains impractical, pushing Cadence and Synopsys to accelerate PQC-aware EDA flows. TSMC is embedding security IP through silicon-proven offerings to fortify its foundry moat, while NVIDIA and Rambus are betting on hardware-accelerated digital signature engines for real-time AI chip authentication. Within 18 months, vendors unable to demonstrate dual resilience—against both quantum cryptanalysis and physical attacks—will be excluded from Western OEM qualification lists, turning supply chain security from a cost center into a regulatory gatekeeper.