IBM Shows Sub-1-nm Chips, Targeting Production in 5 Years

IBM has unveiled its breakthrough in chip manufacturing, introducing the world's first sub-1-nm (0.7-nm) chip technology, with initial production expected from partners within five years. The new 'nan... Read original →

IBM’s 0.7-nm 'nanostack' isn’t a lab stunt—it’s a paradigm shift. By vertically stacking nanosheets, it cracks the SRAM scaling wall that plagues TSMC (Taiwan, China) and Samsung’s current 3D IC approaches, directly cutting data-movement energy in AI chips. This forces high-NA EUV into urgent deployment, pressuring Lam Research to slash multi-patterning costs within two years. Under U.S. CHIPS Act incentives, non-U.S. foundries like Rapidus face steeper barriers as quantum tunneling intensifies yield risks at sub-1-nm nodes. Intel will likely amplify its 'five nodes in four years' narrative, while AI chip firms such as Tenstorrent may pivot to IBM’s ecosystem to bypass memory bottlenecks. Within 18 months, the industry’s metric will shift from transistor density to 'effective compute density'—and leadership hinges on who integrates 3D stacking with novel materials at scale first.