IBM Just Shattered Moore's Law With Sub-1 Nanometer Chips - HotHardware

IBM announced the world's first sub-1 nanometer chip technology on June 25, 2026, marking a significant milestone as the semiconductor industry approaches the physical limits of traditional transistor... Read original →

IBM’s breakthrough transcends mere node shrinkage—it redefines transistor stacking via Nanostack, fusing CFET and GAA into vertically staggered heterostructures that undermine the cost-efficiency assumptions of EUV lithography. This forces EDA, high-aspect-ratio etch tools, and ALD processes to evolve rapidly, challenging TSMC and Samsung’s 2D scaling roadmaps. Geopolitically, U.S. export controls could expand to cover 3D integration equipment within five years, raising compliance costs for foundries in Taiwan, China and Hong Kong, China. Intel may accelerate RibbonFET-PowerVia co-integration, while Rapidus leverages IBM IP to dominate Japan’s AI chip manufacturing. Over the next 18 months, industry metrics will shift from nanometer labels to stacking efficiency—SRAM density and interconnect energy will become critical KPIs. Moore’s Law survives not through planar scaling, but via yield-controlled 3D integration.