Huawei's Tau Law exposes China's EDA gap; Empyrean advances memory chip design tools - digitimes

Huawei's recently proposed Tau Law has sparked industry attention, demonstrating how multi-layer optimization can reduce internal signal transmission time constant τ to improve chip performance. This ... Read original →

Huawei’s Tau Law reveals a systemic gap in China’s EDA stack—particularly in parasitic extraction and multi-physics verification at advanced nodes. This technical pressure has catalyzed Empyrean’s push into memory-specific design tools, attempting to bypass Synopsys’ dominance in logic synthesis. If the U.S. BIS extends export controls to electromagnetic simulation software, Chinese foundries like SMIC and CXMT could face >30% higher tape-out costs. Strategically, Synopsys and Cadence are likely to deepen PDK integration with TSMC’s N2P process, locking out Chinese alternatives. Over the next 18 months, China must choose between accepting suboptimal PPA metrics or committing massive capital to rebuild algorithmic engines and IP libraries from scratch. Without this, its chiplet and advanced packaging ambitions will remain ungrounded.