Huawei chip chief proposes Tau Law V2 centered on time-based scaling

Huawei’s Tau Law V2, pivoting from transistor scaling to time-based compute efficiency, is a strategic architectural bypass of EUV lithography restrictions. This shift pressures EDA vendors, advanced packaging providers, and memory-on-logic innovators to accelerate R&D—particularly benefiting Chiplet and 3D integration ecosystems. However, the absence of peer-reviewed validation introduces significant engineering uncertainty, potentially inflating partners’ verification costs and supply chain compliance burdens. Under sustained U.S. export controls, if widely adopted, this framework could compel TSMC and Samsung to reassess AI chip foundry roadmaps, while NVIDIA may double down on software-defined hardware to retain performance dominance. Within 18 months, concrete efficiency gains from Ascend and Kirin deployments could catalyze a paradigm shift—from transistor density to latency-per-task—as the true inflection point of the post-Moore era.