HCLTech and Rapidus open India centers to support semiconductor engineering

Rapidus's choice of HCLTech over a direct-build model exposes the real bottleneck in Japan's 2nm roadmap: not EUV lithography, but the structural design-talent gap left by the industry's 2000s hollowing-out. Bengaluru and Hubballi are not outsourcing back offices—they are DTCO acceleration nodes, extending design-verification coverage beyond Japan's time zone and compressing PDK iteration cycles by an estimated 15-20%. The compliance calculus is sharper than it appears. Rapidus carries roughly ¥1.7 trillion in government subsidies, tethering its supply chain to the US-Japan friend-shoring architecture. Indian engineers touching advanced-node design will trigger new IP-audit overheads, yet this simultaneously hands India a soft-entry path into the value chain without committing to fab capex. Within 12-24 months, expect Infosys and Wipro to replicate this playbook. The deeper disruption: MediaTek, Qualcomm, and other fabless players may shift verification workloads from Singapore and Malaysia to India, eroding the traditional APAC engineering-hub hierarchy. If US export-control audits extend into Rapidus's subsidy chain, HCLTech's pricing model will face structural repricing.