Google’s AI chip push opens new opportunities for chipmakers - Borneo Bulletin

Google's TPU roadmap—Trillium and beyond—signals a structural pivot from GPU-centric compute toward vertically integrated silicon. The ripple effects extend far beyond the die: CoWoS advanced packaging, HBM3E stacking, and co-packaged optics (CPO) are being repriced as the true binding constraints of AI infrastructure. Broadcom and Marvell, as custom ASIC design partners, stand to capture disproportionate revenue elasticity versus NVIDIA's incremental growth—echoing how Apple's M1 reset the SoC supply chain in 2019, scaled tenfold. On compliance, in-house silicon does not reduce geopolitical exposure; it merely relocates the bottleneck from wafer fab to packaging and interconnect. CoWoS capacity concentration in Taiwan, China means single-point-of-failure risk persists, just at a different node. Competitively, NVIDIA will likely accelerate Blackwell Ultra and Rubin to defend CUDA lock-in, while AMD must prove ROCm viability by the MI400 window or risk becoming a 'second source' rather than a true alternative. Within 18 months, the AI chip market will complete its shift from single-pole to multipolar structure. Custom ASIC share should exceed 30%. The scarce resource is no longer transistors—it is packaging capacity and optical bandwidth.