Google reportedly developing 'Frozen v2' chip with Gemini's architecture etched into the silicon — engineers project 6 to 10 times more tokens per watt than latest TPUs

According to a report by The Information, Google is reportedly developing a server chip codenamed 'Frozen v2,' which would integrate parts of the Gemini model's architecture directly into the silicon.... Read original →

Google’s 'Frozen v2' initiative represents a paradigm shift: hardcoding AI architecture—not weights—into silicon redefines inference chip design. This forces EDA vendors to enable pre-silicon validation of neural topologies and pressures cloud providers to rethink TPU ecosystem compatibility. Geopolitically, reliance on TSMC’s 3nm EUV capacity in Taiwan, China exposes supply chain fragility; any U.S. export control expansion on advanced packaging could accelerate Google’s pivot toward Intel. NVIDIA will likely counter with enhanced dynamic sparsity in Blackwell Ultra, while startups like Taalas may exploit open-architecture niches. Within 18 months, hyperscalers will broadly adopt ‘fixed-architecture, updatable-weights’ chips, transitioning AI accelerators from general-purpose engines to model-specific co-processors—and resetting the energy-efficiency battleground in data centers.