GlobalFoundries VP details FDX Fusion technology, sporting 7nm-class performance without the need for EUV tools — company targets 2030 for high-volume manufacturing, with planar transistors in tow - Tom's Hardware

GF's FDX Fusion is not a technical compromise—it is a formal declaration of an EUV-free process roadmap. Post-ASML export restrictions, DUV multi-patterning has shifted from fallback to strategic necessity. Choosing planar transistors over GAA looks like architectural regression, but it is a rational ~40% capex reduction per wafer. 7nm-class automotive MCUs and industrial SoCs demand cost-per-performance, not leakage-floor physics. Upstream impact: this route will directly pull ASML NXT:2050i and Nikon NSR-S636E DUV orders, forcing Synopsys and Cadence to recalibrate 7nm-class PDK models. More critically, it validates that DUV plus planar/FinFET retains two to three generations of headroom before physical limits—shattering the industry axiom that no EUV means no advanced node. Competitive dynamics: TSMC and Samsung will not follow below 3nm, but SMIC's 7nm DUV process serves as a live stress-test for GF's approach. GF's real battleground is the long tail—of the 60+ billion automotive and industrial chips shipped annually, 70% sit in the 28nm-to-7nm band. That is FDX Fusion's true TAM. 12-24 month outlook: expect automotive chip designers to lock in FDX Fusion IP licenses by H2 2025; ASML's DUV revenue share to climb from ~35% to 45%+; and de-EUV-ification to transition from policy narrative to a quantifiable TCO model embedded in EDA toolchain defaults.