Full-pose self-calibrated table-top EUV grazing-reflection ptychography | Newswise - Newswise

This work tackles a fundamental bottleneck in EUV semiconductor metrology: the calibration complexity inherent to reflection-mode ptychography in tilted-detection geometries. As EUV lithography advanc... Read original →

The strategic weight here is not the 43.5-nm figure but what it decouples: metrology fidelity from hardware precision. For two decades, EUV inspection economics have been anchored to ASML's alignment infrastructure and KLA's CD-SEM installed base. Absorbing geometric uncertainty into a differentiable forward model—solved by software rather than sub-nanometer stages—restructures the cost curve of wafer metrology from the ground up. Upstream, dependency on precision positioning (Heidenhain, Renishaw) erodes. Downstream, sub-2nm fabs gain a non-destructive, in-line complement that slots between CD-SEM and e-beam without displacing either. Real-chip validation marks the inflection: this is no longer a physics demo. KLA's $5B metrology franchise assumes proprietary hardware is the moat. A geometry-agnostic, openly published algorithm compresses that moat. Expect defensive patent filings within two quarters and ASML to bundle a ptychography module into NXT:CAM. The table-top form factor, however, targets process-engineering labs and 3D heterogeneous integration inspection—territory KLA has historically under-served. For China's domestic fabs, an algorithmic (not hardware) metrology capability is inherently export-control-resistant. Within 18 months, expect at least one pilot deployment in 3D-IC inspection where destructive cross-section remains the binding constraint.