From Spec To Formal Properties

As artificial intelligence advances, its application in semiconductor design and verification is growing. This article explores the process of transforming design specifications into formal properties... Read original →

The transformation from natural language specifications to formal properties is fundamentally reshaping semiconductor verification workflows. While AI tools accelerate property generation, their reliance on complete and unambiguous specs reveals systemic risks. Current LLMs struggle with incomplete or ambiguous documentation, often producing logically weak but syntactically valid properties, necessitating human review and validation. This shift forces a reevaluation of verification environments, with upstream EDA vendors like Synopsys and Siemens EDA needing to integrate knowledge graphs with formal methods more deeply. Downstream design firms face pressure to restructure their verification infrastructures. Geopolitical tensions, especially in Taiwan and Hong Kong, are pushing companies toward localized verification capabilities. In the short term, a tiered tool market will emerge, with high-end platforms competing for technical dominance, while mid-tier players may be phased out due to cost pressures. Within 12 months, intelligent verification workflows will accelerate, but widespread adoption of formal methods will still encounter cultural and engineering resistance.