Fraunhofer IPMS advances chiplet integration and low-power memory ... - eeNews Europe

Fraunhofer IPMS's move is not academic curiosity—it is Europe's bid to seize pricing power in the 'packaging-defines-the-chip' era. Technical ripple: coupling chiplets with low-power memory targets the energy ceiling of AI inference. Once compute and memory dies decouple, hybrid-bonding yield and UCIe interconnect bandwidth become the new chokepoints. ASML's bonding tools and Synopsys's die-to-die IP capture first-mover upside. Compliance and risk: public-research-led output will likely flow into open patent pools, systematically eroding commercial players' packaging moats. Yet U.S. export controls on advanced bonding equipment remain a hard constraint on Europe's lab-to-fab transition. Market dynamics: Intel's open EMIB, TSMC's closed CoWoS, and Samsung's X-Cube vertical stack will all be forced to accelerate standardization. If low-power memory escapes HBM's single-architecture lock, SK Hynix's pricing leverage gets structurally diluted. 12–24 month outlook: chiplet architecture migrates from AI accelerators into automotive and edge silicon. 'Selling functional modules' replaces 'selling wafers'—the semiconductor business model's underlying logic is being rewritten.