Foundry 2.0 revenue hits record as growth spreads beyond TSMC

The $96.6B Foundry 2.0 figure signals a structural shift in where value accrues, not merely a demand spike. For a decade, foundry margins anchored to the most advanced transistor; TSMC captured over 70% of industry profit on 3nm/2nm. But this AI infrastructure cycle reveals an underappreciated truth: the bottleneck has migrated to power delivery ICs, high-speed SerDes, and HBM packaging—all in the 28nm–250nm mature band. The technical cascade is structural. In an AI accelerator BOM, leading-edge logic is a minority cost line; value density concentrates in CoWoS-class packaging, PDN, and interconnect. GlobalFoundries, UMC, and Samsung Foundry will sustain 85%+ utilization on 28–90nm nodes for years, while advanced-packaging players gain pricing power that historically belonged to pure-logic foundries. On compliance, CHIPS Act and EU subsidies are fragmenting mature-node capacity geographically; an 18-month window of regional overcapacity is highly probable. The real moat is no longer the node—it is vertical integration across packaging, test, and system-level assembly. Competitively, TSMC's near-monopoly is eroding. Intel Foundry leverages Foveros for AI interconnect; Samsung bundles 2nm GAA with HBM to lock in hyperscaler orders; UMC and PSMC clash head-on with TI and MPS in power management. 12–24 month outlook: Foundry 2.0 gross margins will compress as capacity catches up, but advanced packaging and SiP premiums will widen. The industry is pivoting from a smallest-transistor arms race to a most-complete-system-integration ecosystem war.