Former Intel CEO's Latest Judgment: Vast Majority of Chip Design Firms Will Vanish, Manufacturing Stands As The Only Core Moat - 36Kr

This isn't a dismissal of design—it's a recognition that fabless margin is being crushed by three converging forces: process standardization, IP commoditization, and geopolitical fragmentation. Technical cascade: Once GAA and CFET architectures are replicated across TSMC, Samsung, and Intel within two to three nodes, the design innovation window compresses from 18 months to six. The moat shifts from 'drawing well' to 'fabricating reliably'—CoWoS throughput, yield curves, overlay precision. These are physics problems no GDSII file can solve. ASML's EUV delivery cadence now dictates who stays at the table. Compliance exposure: The CHIPS Act and EU Chips Act are, in substance, fiscal mandates to regionalize manufacturing. A design house without captive wafer capacity is structurally naked when export controls tighten. At sub-2nm, wafer costs exceed $20,000; NRE spend that doesn't convert to production yield kills cash flow within a year. Strategic positioning: TSMC's pricing leverage hardens. Mid-tier fabless firms ($500M–$2B revenue) face existential compression. Intel's IDM 2.0 bet is validated. NVIDIA and AMD will likely lock 2026–2027 CoWoS capacity rather than build fabs. Taiwan, China's UMC and PowerChip are being squeezed into mature nodes. 12–24 month outlook: Expect a 30%+ reduction in active fabless players globally. M&A logic pivots from 'acquire IP' to 'acquire capacity.' RISC-V's open-source narrative cannot substitute for the physical barrier of a fab—without one, an open architecture is just a blueprint.